1. Field of the Invention
The present invention generally relates to logic books for use in very large scale integrated (VLSI) circuit design and, more particularly, to novel technology logic books with mixed low and regular voltage threshold (V.sub.t) metal oxide semiconductor field effect transistor (MOSFET) devices in the deep sub-micron regime.
2. Background Description
Speed and power are of utmost concern in deep sub-micron VLSI circuit design. These two competing requirements typically must be resolved with design tradeoffs by the VLSI circuit designer to obtain an optimum design. As the channel lengths of transistors used in VLSI circuits are scaled into the deep submicron regime, typical operating voltage (V.sub.dd) drops to less than two volts (2V). See for example the following references:
R. H. Dennard, F. H. Gaensslen, H. N. Yu, V.sub.t L. Rideout, E. Bassous, and A. R. LeBlanc, IEEE Journal of Solid-State Circuits, vol. 9, No. 5, 256 (1974) PA0 B. Davari, R. H. Dennard, and G. G. Shahidi, Proceedings of the IEEE, vol. 83, No. 4, 595 (1995) PA0 Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S. H. Lo, G. A. Sai-Halasz, R. G. Wiswanathan, H. J. C. Wann, S. J. Wind, and H.
S. Wong, Proceedings of the IEEE, Vol. 85, No. 4, 486 (1997)
To keep devices' off-current at a reasonable level, the threshold voltage (V.sub.t) is maintained at a level of 300 to 400 millivolts (mV). See L. Su, S. Subbanna, E. Crabbe, P. Agnello, E. Nowak, R. Shulz, S. Rauch, H. Ng, T. Newman, A. Ray, M. Hargrove, A. Acovic, J. Snare, S. Crowder, B. Chen, J. Sun, and B. Davari, 1996 Symposium on VLSI Technology Digest of Technical Papers, p. 13, Honolulu, Jun. 11-13, 1996. The performance (or speed) of a VLSI system such as a high-performance microprocessor is closely linked to the value of overdrive (V.sub.dd -V.sub.t). To the first approximation, an inverter's delay (t.sub.d) is: ##EQU1## where n=V.sub.t /V.sub.dd, .beta.=.mu.C.sub.ox W/L, and .mu. is electron (or hole) mobility depending on the switching off (or on) situation being considered, C.sub.ox is the gate capacitance, W/L is the width-to-length ratio, and C.sub.L is the load capacitance. See N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, .sub.2 nd Edition, Addison Wesley, Chapter 4, 1994. To gain performance with complementary metal oxide semiconductor (CMOS) technology, there has been a need for making low V.sub.t MOSFETs. This gain will become larger and larger as V.sub.dd continues to be scaled down. See Y. Taur et al., ibid. In CMOS circuits, a typical low V.sub.t device in current technology would have a V.sub.t of 250 mV that is about 100 mV lower than the regular V.sub.t devices, and typical gains estimated from the above formula are about 10%, which is in good agreement with simulation. See L. Su et al., ibid. However, the low Vt devices typically have much higher leakage current than the regular devices (5 to 10 times higher). This high leakage current, among other considerations, inhibits wide-spread-use of low V.sub.t devices in a VLSI design.
One approach to circumvent this limitation that has been adopted is to make low V.sub.t static logic books such as NAND, NOR, and other logic gates and blocks composed of all low-V.sub.t devices, and implement them only in the critical path part of the circuits. Even though a single low V.sub.t logic book would indeed give rise to much higher stand-by power, speed can still be gained without increasing too much system's standby power because the book count of the critical paths is only a small fraction of the total book/device count of the system. By definition, a logic book in the current writing means a basic logic unit/block, such as NAND and NOR gates, a combination of AND and OR gates and inverters (NAND and NOR gates), or a logic block such as an ADDER, MULTIPLEXER or BUFFER, which performs a certain logic function and is treated as a unit by high level circuit/logic or system designers.
The much higher leakage currents of low V.sub.t logic books in some critical parts of a design to gain speed is a particular concern in the deep submicron regime of VLSI circuit design. This concern about high leakage current along with other considerations limits the use of low V.sub.t logic books in the design. This is especially true when the millions of transistors used in current generation microprocessors already dissipate tens of watts of power on a single chip. The problem therefore presented for designers of the next generation of VLSI circuits is whether low V.sub.t and regular V.sub.t devices can be mixed in a single logic book in some fashion that will permit a gain in speed without a significant increase in standby power.